1. Field of the Invention
The present invention relates to a protecting circuit for a semiconductor circuit, in particular, to a protecting circuit connected to an input terminal and an output terminal.
2. Description of the Related Art
Whenever semiconductor apparatuses are handled, in every situation such as fabrication, assembling, and operation, they should be potected against a breakdown due to static electricity. Static discharging results, for example, in deterioration of characteristics, breakdown of a junction, and damage of an oxide film. In recent years, the semiconductor devices have been drastically miniaturized. However, the miniaturization of semiconductor devices causes the resistance against the breakdown due to static electricity to deteriorate. Thus, countermeasures against the static discharging are becoming important.
In the most common example of a breakdown due to static electricity, static electricity that has been charged to a human body causes static discharge. On occasion, the charged voltage may amount to several 1000 V. This discharging may cause, for example, an electrode of a semiconductor device to melt, a P-N junction to break, and an oxide film to break down.
A semiconductor apparatus using MOS transistors has a gate electrode that is insulated from the transistors. Thus, especially, this semiconductor apparatus does not have a sufficient resistance against the breakdown due to static electricity. Consequently, countermeasures against static electricity are required. As a conventional method of such countermeasures, a protecting circuit is disposed between an input terminal and an input circuit so that the protecting circuit absorbs an excessive voltage.
A protecting circuit is composed of a resistor, a p-n diode, a combination of a resistor and a p-n diode, a combination of a resistor and a MOS diode, and so forth.
FIG. 7A is an equivalent circuit showing an example of the structure of a conventional static electricity protecting circuit of such a semiconductor apparatus. Referring to FIG. 7A, the protecting circuit comprises a p channel type MOS transistor P1 and an n channel type MOS transistor N1. A source electrode, a gate electrode, and a substrate electrode of the p channel type MOS transistor P1 are connected to a high voltage power supply VDD. A source electrode, a gate electrode, and a substrate electrode of the n channel type MOS transistor N1 are connected to a low voltage power supply VSS. A drain of the p channel type MOS transistor P1 and a drain of the n channel type MOS transistor N1 are connected. This connected point is connected to an external terminal and an internal circuit of a semiconductor integrated circuit.
FIG. 7B is a sectional view showing the structure of the protecting circuit shown in FIG. 7A. Referring to FIG. 7B, a source electrode S1 and a gate electrode G1 of a p channel type MOS transistor P1 formed in an n well region on a p type substrate are connected to a high voltage power supply VDD with a metal wire M1. In addition, the source electrode S1 and the gate electrode G1 are connected to the n well region with a contact C1.
On the other hand, a gate electrode G2 and a source electrode S2 of the n channel type MOS transistor N1 are connected to a low voltage power supply VSS with a metal wire M3. In addition, the gate electrode G2 and the source electrode S2 are connected to a p type substrate with a contact C2.
The drain electrode D1 of the p channel type MOS transistor P1 and the drain electrode D2 of the n channel type MOS transistor N1 are connected to an external terminal and an internal circuit with a metal wire M2. These transistors P1 and N1 are isolated with a field oxide film SiO.sub.2. An oxide film is formed on the front surface of these devices including individual electrodes so as to insulate the metal wires from the electrodes of the devices.
When a voltage that is higher than a power supply voltage is applied to the external terminal, the voltage of the n channel type MOS transistor N1 becomes higher than a threshold value and thereby a current flows in the n channel type MOS transistor N1. In contrast, when a voltage lower than VSS is applied to the external terminal, a current flows in the p channel type MOS transistor P1. When an abnormal voltage is applied to the external terminal, a current flows in the n channel type MOS transistor N1 or the p channel type MOS transistor P1 so as to protect the internal circuit.
A pnp type parasitic bipolar transistor Tr1 is formed between the source electrode and the drain electrode of the p channel type MOS transistor P1. A npn type parasitic bipolar transistor Tr2 is formed between the source electrode and the drain electrode of the n channel type MOS transistor N1.
The base voltage of the parasitic transistor Tr2 on the n channel side becomes equal to the voltage of the channel portion ch2. However, since the base electrode and the contact C2 is spaced to some extent, a parasitic resistance R2 takes place therebetween.
When an excessive plus voltage is applied to the drain electrode D2 of the n channel type MOS transistor N1 against the low voltage power supply VSS, an avalanche breakdown current flows at a connection between the n type drain electrode D2 and the p type substrate sub.
Since the resistance of the parasitic resistor R2 is not zero, the voltage of the channel portion ch2 (namely, the base voltage of the parasitic transistor Tr2 rises). Thus, the parasitic transistor Tr2 snaps back. FIG. 2 is a graph showing the relation between a source-drain voltage VDS and a source-drain current IDS upon occurrence of snap-back phenomenon. Referring to FIG. 2, the voltage VSBN at which the parasitic transistor Tr2 has snapped back is lower than the voltage BVDSS at the initial stage of the avalanche breakdown.
Thus, the parasitic transistor Tr2 clamps the excessive voltage to the voltage VSBN at which it has snapped back. Likewise, the parasitic transistor Tr1 on the p channel side clamps the excessive voltage to VSBP.
Experimental results of breakdown withstand voltages against static surge and so forth show that parasitic transistors more easily break down in the case that an n channel type transistor snaps back than the case that a p channel type transistor snaps back.
In other words, since a parasitic transistor formed in an n channel type MOS transistor N1 is of npn type, after the parasitic transistor snaps back, it tends to locally heat and break down. Since electrons in a device have higher mobility than holes therein, an npn transistor tends to snap back. In addition, the amplitude hfe of the parasitic transistor largely depends on the temperature. Thus, current and heat tend to concentrate in the parasitic transistor, resulting in a breakdown thereof.
In addition, since two types of an n channel type MOS transistor and a p channel type MOS transistor are used in the protecting circuit, it is difficult to reduce the size thereof.
In other words, since impurities of the drain electrode and the source electrode of an n channel type MOS transistor are different from those of a p channel type MOS transistor, the drain electrode and the source electrode cannot be formed in common.